Advancements in LSI (“Large Scale Integrated”) technology continuously bring about reduced transistor sizes and corresponding many-fold increase in the number of transistors that can be mounted on a single chip. However, even though power supply voltage has been lowered considerably, the combination of size and transistor count is such that chip power consumption continues to grow resulting in increased concern with power consumption and dissipation. Power consumption and dissipation concerns have become a limiting factor in the design of LSIs used in microprocessors and other devices that require large-scale, high-speed processing. Thus, reducing power consumption has become a major priority throughout the field of LSI-related development, ranging from computer systems to circuit and device technologies.
Attempts to limit power consumption while reducing power source voltage that have been made so far have however resulted in a decline in transistor drive capability resulting in reduced operating speed. This trade off is not generally acceptable. As a result, there is a pressing need for circuit technology that can reduce energy consumption as well as source voltage without sacrificing operating speed.
Charge recycling provides a mechanism that offers a solution by utilizing charge stored in the distributed capacitance of one or more circuit nets to charge other nets that are at an opposing potential, during intermediate idle periods. This process of charge equalization, allows for a mutual exchange of energy when the data lines are transitioning thereby effectively enabling reuse of electrical power—and consequent reduction in overall power consumption.
Existing methods of charge redistribution are capable of operating with dual rail charge redistribution systems, in which paired complementary signal nets exchange charge locally. To take advantage of the charge redistribution for digital systems, it is mandatory with the present technologies to introduce an extra complementary line with each signal line. This introduction of extra complementary lines results in increased coupling capacitance and increased size of the chip which is undesired. In the case of Deep Sub-Micron (“DSM”) technology the increase in coupling capacitance results in a significant increase in the total capacitance thereby resulting in undesirable consequences of reduces operation speed and increased power consumption it is therefore, more important in DSM systems to have a charge redistribution system that does not required the addition of complementary signal lines.